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commercial temperature range november 1996 ?1996 integrated device technology, inc. dsc-2066/5 8.03 1 ? supports up to 4 phys for multi-phy connections with 2- bit address and 8-bit data using utopia 2 protocol. ? provides an 8-bit microprocessor bus interface for configuration, control and monitoring. ? low power cmos ? 128 pin pqfp package (14 mm x 20 mm). description the IDT77155 is a member of idt's switchstar ? family of products for asynchronous transfer mode (atm) net- works. the IDT77155 is a integrated circuit that provides the sonet/sdh processing and atm mapping functions of a 155 mbps/51 mbps atm user network interface. provides full compliance with sonet/sdh requirements and atm forum integrated device technology, inc. nicstar is a trademark and the idt logo is a registered trademark of integrated device technology, inc. phy (tc-pmd) user network interface for 155 mbps atm network applications advanced information IDT77155 key features ? one chip atm user network interface for 155.52 mbps/ 51.84mbps operating speed. ? full implementation of the sonet/sdh criteria according to bellcore gr-253-core and itu-t g.709, g.783. ? full implementation of the atm physical layer according to ccitt i.432 and atm forum user network interface specification. ? full-duplex 155.52 mbps sts-3c/stm-1 or 51.84 mbps sts-1 data with built-in clock/data recovery and clock synthesis. ? supports 4-cell phy fifo buffers for both transmit and receive directions with parity. ? provides gfc bits insertion and extraction. ? utopia level 1 and level 2 interface. system-level functional block diagram encoder parallel to serial transmit sonet framer clk gen. transmit atm cell fifo clk rec. serial to parallel receive sonet framer decoder receive utopia cell fifo encoder clk rec. rrclk+ rrclk- alos+ alos- rxd+ rxd- rxdo+ rxdo- rbyp rclk rgfc rca txaddr[1:0] trclk+ trclk- txd+ txd- txc+ txc- tbyp rate0 tclk tcp transmit utopia cell fifo mphyen apt1 lf lf+ lfo ralm rfp rcp atp2 rate1 tfpo xoff tgfc tca tsoc tdat[7:0] txprty tfclk rsoc rdat[7:0] rxprty rfclk tsen rxaddr[1:0] 3497 drw 01 micoprocessor interface d[7:0] a[7:0] ale
8.03 2 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range gnd gnd IDT77155 top view px-128 3497 drw 02 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 tbyp atp2 avcc agnd avcc agnd avcc trclk- trclk+ agnd txvcc txc+ txc- txd+ txd- txgnd vcc gnd vcc gnd rxdo+ rxdo- avcc rxd- rxd+ alos- alos+ agnd avcc agnd avcc rrclk- rrclk+ agnd avcc agnd gnd 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 102 101 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vclk rate[0] rate[1] tsoc txprty tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] tca tfclk rsoc rxprty vcc gnd rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] vcc gnd rdat[1] rdat[0] rca rfclk tsen gnd gnd ale a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] d[7] d[6] d[5] d[4] vcc gnd d[3] d[2] d[1] d[0] vcc gnd gnd gnd atp1 rbyp lf+ lf- lfo rxaddr[1] rxaddr[0] txaddr[1] txaddr[0] mphyen xoff tcp tgfc tfpo tclk vcc gnd rclk rfp rgfc rcp vcc gnd ralm gnd 104 103 user network interface specifications. the IDT77155 provides both transmission convergence (tc) and physical media dependent (pmd) sublayer func- tions of a 155.52 mbps/51.84 mbps atm phy suitable for atm networks. the sonet/sdh interface provides the sonet/sdh overheads demultiplex and multiplex process- ing functions. the utopia interface provides standardized control and communications to other components, such as segmentation and reassembly (sar) controllers and atm switches. the IDT77155 is fabricated using state-of-the-art cmos technology, providing the highest levels of integration, perfor- mance and reliability, with the low-power consumption char- acteristics of cmos. package pinout
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 3 package dimensions dimensions dimensions dimensions dimensions dimensions 128-pin pqfp dimension tolerance dimension letter (mm) (mm) a max. 3.30 a1 +.10 0.35 a2 +.17 2.70 d +.25 17.20 d1 +.10 14.00 e +.25 23.20 e1 +.10 20.00 l +15 0.75 e basic 0.50 b .05 0.22 8'-7" 9'-5" e1 e 1 128 128-pin pqfp 6'-8" d 5'-10" d1 2'-0" b 4 4 l a a2 e draft angle = 11 ?3 a1 0.20 rad typ. 0.20 rad typ. 3445 drw 03
8.03 4 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range symbol name i/o description a0-a7 address i address bus to select specific registers in the register set. the address pin a7 has an integral pull-down resistor. pin #: a0/119, a1/120, a2/121, a3/122, a4/123, a5/124, a6/125, a7/126 agnd analog ground g these pins should be physically isolated from the other ground pins. pin #: 5, 7, 11, 29, 31, 35, 37 ale address latch i latches the address bus when low, and is transparent when high. it allows interfacing to a enable multiplexed address/data bus. ale has an integral pull-up resistor. pin #: 127 alos+ analog loss of i differential inputs indicate a loss of receive signal power. when alos+/- is asserted, data alos- signal on the rxd+/- inputs is squelched and the receive data/clock recovery pll switches to the reference clock. alos+/- has an effect only when rbyp is disabled. these inputs must be dc-coupled. pin #: alos+ 28, alos- 27 atp1 test pin i test pin for the transmit clock synthesis logic. when asserted, the tnb output of the clock synthesis block is reflected on the lfo pin. atp1 has an integral pull-down resistor. pin #: 40 atp2 test pin i test pin for the receive clock/data recovery logic. when asserted, the cnb output of the clock recovery block is reflected on the lf-pin. atp2 has an integral pull-down resistor. pin #: 3 avcc analog power p these power pins should be physically isolated from the other power pins and connected to a well coupled 5v dc source. pin #: 4, 6, 8, 24, 30, 32, 36 cs chip select i active low chip select to access registers. pin #: 100 d1-d7 data i/o bidirectional data bus for register access during register reads and writes. pin #: d0/109, d1/110, d2/111, d3/112, d4/115, d5/116, d6/117, d7/118 gnd ground g core, ring and thermal grounds. pin #: 1, 19, 21, 38, 39, 56, 62, 64, 65, 72, 80, 102, 103, 106, 113, 128 int interrupt o open drain interrupt signal which goes low when an interrupt source is active and unmasked open from within the chip. this signal is cleared by appropriate reads to the interrupt registers. int is an open-drain output. pin #: 108 lf+ loop filter o special pin to output cap voltage of the receive data/clock recovery logic when atp2 is lf- enabled. reference clock signal of the receive data/clock recovery logic. pin #: lf+/42, lf-/43 lfo special o special pin to output cap voltage of the transmit clock synthesis logic when atp1 is enabled. pin #: 44 mphyen multi-phy enable i when asserted, the multiphy enable signal converts the utopia interface to be fully compliant with the utopia level-2 specification. in this mode, the txaddr[1:0] and rxaddr[1:0] bits determine the address of the device to be addressed. the default operation of the chip is in single-phy utopia level-1 mode. mphyen pin has an integral pull- down resistor. pin #: 49 ralm receive alarm o output is asserted if line alarm indication signal (lais), path alarm indication signal (pais), loss of signal (los), loss of frame (lof), or loss of cell delineation (loc) is detected in the receive logic. ralm is updated on the rising edge of rclk. pin #: 63 rate0 line rate i rate inputs select the frame format and line rates for both the transmit and receive functions rate1 rate(1:0) 11 155.52 mb/s, sts-3c / stm-1 10 51.84 mb/s, sts-1 0x reserved the rate inputs have integral pull-up resistors, so the default is sts-3c pin #: rate0/98, rate1/97 pin descriptions
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 5 symbol name i/o description rbyp receive bypass i active high rbyp input disables clock recovery. if enabled, the receive different serial data rxd+/- is sampled on the rising edged of the receive differential reference clock rrclk+/-. if rbyp is disabled, the receive clocks are recovered from rxd+/- bit stream. rbyp has an integral pull down resistor. pin #: 41 rca/ receive cell o this signal is asserted to indicate either 0 or a maximum of 4 morebytes are present in the rxempty available tristate receive fifo. the indication of the receive fifo level is programmable, as is the polarity of this signal. signal is updated on the rising edge of rfclk. the rca signal is tristated in utopia level-2 mode (mphyen asserted) and driven as per the multi-phy protocol. pin #: 69 rclk receive clock o provides a timing reference, and is a divide-by-8 version of tri-covered clock when rbyp is disabled or rrclk+/- when rbyp is enabled. pin #: 57 rcp receive cell o receive gfc pulse indicates the start of the four generic flow control bits (gfc) in the rgfc pulse output. rcp is coincident with the most significant gfc bits. rcp is updated on the rising edge of rclk. pin #: 60 rd read i active low read signal to read contents of addressed register. the data bus is driven by the contents of the addresses register when the read signal is asserted along with the chip select (cs) signal. pin #: 105 rdat0- receive data o the receive cell data to the atm layer from the receive fifo. this is updated on the rising rdat7 edge of rfclk. rdat[7:0] is tristated if tsen is asserted or if mphyen is asserted. in utopia single-phy mode, it is driven if rrdenb is asserted (tsen also asserted) or always driven if tsen is low. in utopia multi-phy mode, rdat[7:0] is driven following the level-2 protocol. pin #: rdat0/70, rdat1/71, rdat2/74, rdat3/75, rdat4/76, rdat5/77, rdat6/78, rdat7/79 rfclk receive fifo i the receive atm clock from the atm layer <= 40 mhz. the start of cell indication, the clock transmit data, and the transmit data parity signals are updated on the rising edge of this clock. rrdenb is sampled on the rising edge of this clock. pin #: 67 rfp receive frame o an 8 khz signal synchronized to rclk. it is pulse high for one clock every 2430 rclk pulse cycles for sts-3c or every 810 rclk cycles for sts-1. it is updated on the rising edge of rclk. pin #: 58 rgfc receive generic o outputs the extracted generic flow control bits (gfc) in a serial stream. the four gfc bits flow control are output for each receive cell, and the first of the four bits is coincident with the rcp output, rgfc is low until cell delineation is achieved. rgfc is updated on the rising edge of rclk. pin #: 59 rrclk+ receive differential i inputs contain a jitter-free 19.44 mhz or a 6.48 mhz reference clock when clock recovery rrclk- reference clock is enabled (rbyp = 0). when rbyp is enabled, rrclk+/- is nominally a 155.52 mhz or 51.84 mhz 50% duty cycle clock and provides the timing for the internal receive functions. rxd+/- is sampled on the rising edge of rrclk+/- pin #: rrclk+/34/ rrclk-/33 rrdenb receive read i active low signal from atm signifying that data will be sampled on rdat[7:0] in the enable following clock cycle. when sampled high, rsoc and rdat[7:0] are tristated, if tsen is enabled. rrdenb must operate with rfclk at high rate to prevent receive fifo overflow and loss of receive data. pin #: 68 pin descriptions (continued)
8.03 6 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range symbol name i/o description rsoc receive start o indication to the atm layer. this is asserted during the first byte of each tristate cell and is of cell updated on the rising edge of rfclk. rsoc is tristated if tsen is asserted or if mphyen is asserted. in utopia single-phy mode, it is driven if rrdenb is asserted (tsen also asserted) or always driven if tsen is low. in utopia multi-phy mode, rsoc is driven following the level-2 protocol. pin #: 83 rst reset i active low asynchronous reset from the system. rst has integral pull-up resistor. rst need not be asserted to reset the chip. pin #: 101 rxaddr[0] receive address i receive address indicates the id of the device which should respond to the receive bus rxaddr[1] signals in utopia level-2 multi-phy mode (when mphyen is asserted). it indicates the device which should drive the receive cell to atm device. the device id may be programmed in a receive id register. the device id register contain a default address of 0. rxaddr[1:0] is sampled on the rising edge of rfclk. rxaddr[1:0] inputs have integral pull-up resistors. rxaddr[1:0] inputs are ignored when mphyen is not asserted. pin #: rxaddr0/46, rxaddr1/45 rxd+ receive i nrz encoded receive differential data inputs which contain sts-3c or sts-1 data, and rxd- differential sampled on the rising edge of rrclk+/- if rbyp asserted, else the receive clock are data inputs recovered from the data stream. pin #: rxd+/26, rxd-/25 rxdo+ receive o sliced versions of the rxd+/- inputs, to allow decision feedback equalization (dfe) to rxdo- differential correct baseline wander. these outputs could be programmed to be pure pecl. defaults is a data outputs rail-to-rail swing. pin #: rxdo+/22, rxdo-/25 rxprty receive parity o indicates the parity of the rdat[7:0] bus. odd or even parity may be selected. tristate rxprty is enabled on the rising edge of rfclk, rxprty is tristate if tsen is asserted or if mphyen is asserted. in utopia single-phy mode, it is driven if rrdenb is asserted (tsen also asserted) or always driven if tsen is low. in utopia multi-phy mode, rxprty is driven following the level-2 protocol. pin #: 82 tbyp transmit bypass i active high transmit bypass input disables clock generator. if enabled, the clock inputs trclk+/- become the transmit line lock at 155.52 mhz or 51.84 mhz. if disabled, the transmit clock is synthesized from a 19.44 mhz or 6.48 mhz reference clock on trclk+/-. tbyp has an integral pull down resistor. pin #: 2 tca/ transmit cell o signal indicates the availability of a complete cell space in the transmit fifo. this signal txfull available when asserted indicates a maximum of 4 more transmit data writes will be accepted or that the transmit fifo is full and no more writes will be accepted. the indication of the transmit fifo level is programmable, as is the polarity of this signal. the fifo depth at which the tca signal indicates the unavailability of data space in the fifo may be set to one, two, three, or four cells. tca is updated on the rising edge of tfclk. pin #: 86 tclk transmit clock o the transmit byte clock provides a timing reference, and is a divide-by-8 version of the synthesized clock when tbyp is disabled or trclk+/- when tbyp is enabled. pin #: 54 tcp transmit cell o transmit gfc cell pulse indicates the expected place of the transmit gfc bits. tcp is pulse updated on the rising edge of tclk. pin #: 51 tdat[0]- transmit cell i the transmit cell data from the atm layer sampled on the rising edge of tfclk. it carries tdat[7] data the 53 cell bytes. it is considered valid only when the twrenb signal is asserted. pin #: tdat0/87, tdat1/88, tdat2/89, tdat3/90. tdat4/91, tdat5/92, tdat6/93. tdat7/94 tfclk transmit fifo i the transmit atm clock from the atm layer <= 40 mhz. the start of cell indication, the clock transmit data, the transmit data parity, and the enable signals are sampled on the rising edge of this clock. pin #: 84 pin descriptions (continued)
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 7 symbol name i/o description tfpo transmit framing o transmit frame pulse is an 8 khz signal synchronized to tclk. it is pulsed high for one position output clock every 2430 tclk cycles for sts-3c or every 810 tclk cycles for sts-1. it is updated on the rising edge of tclk. pin #: 53 tgfc transmit generic i input provides the ability to insert gfc values downstream of the transmit fifo. the four flow control tclk periods following tcp output pulse should contain the four gfc bits to be inserted. the gfc enable bits in a configuration register enable the insertion of each bit. by default, the gfc values contain the header information of the default idle/unassigned cell header register. the inserted gfc bits are input into the next immediate cell to be transmitted. tgfc bits are sampled on the rising edge of tclk. pin #: 52 trclk+ transmit i differential input contain a jitter-free 19.44 mhz or a 6.48 mhz reference clock when clock trclk- reference clock synthesis is enabled (tbyp = 0). when tbyp is enabled, trclk+/- is nominally a 155.52 mhz or 51.84 mhz 50% duty cycle clock and provides the timing for the internal transmit functions. it may be left unconnected if loop timing is enabled. pin #: trclk+/10, trclk-/9 tsen transmit enable i the tristate enable signal tristates rsoc, rdat[7:0], and rxprty signals. when asserted, rsoc, rdat[7:0], and rxprty are driven only when rrdenb is asserted. when tsen is low, the signals rsoc, rdat[7:0], and rxprty, are always asserted in single-phy utopia level-1 mode. tsen has an integral pull-down resistor. pin #: 66 tsoc transmit start of i the transmit start of cell indication from atm layer. this should be asserted during the first cell byte of each cell and is sampled on the rising edge of tfclk. an interrupt is generated while tsoc is asserted at any byte other than the first byte of the transmit 53 byte cell. pin #: 96 twrenb transmit write i active low transmit enable signal used to initiate writes to the transmit fifo from the atm enable device. when asserted low, the byte on tdat[7:0] is written to the transmit fifo. a complete 53 byte cell must be written to the fifo before the cell is inserted into the spe of the transmit frame. idle/unassigned cells are inserted until a complete cell is available for transmission. pin #: 85 txaddr[0] transmit address i indicates the id of the device which should respond to the transmit bus signals in txaddr[1] transmit bus signals in utopia level-2 multi-phy mode (when mphyen is asserted). it indicates the device which should accept the transmit cell from atm device. the device id may be programmed in a transmit id register. the device id register contain a default address of 0. txaddr[1:0] is sampled on the rising edge of tfclk. txaddr[1:0] inputs have integral pull-up resistors. txaddr[1:0] inputs are ignored when mphyen is not asserted. pin #: txaddr0/48, txaddr1/47 txc+ transmit clock o transmit differential line negative output clock is a buffered version of the input differential txc- clock. these outputs could be programmed to be pure pecl. default is a rail-to-rail swing, if these outputs are not programmed to be pecl, then the outputs are squelched in the sts-3c mode. pin #: tsc+/13, txc-/14 txd+ transmit data o nrz encoded transmit differential data outputs which contain sts-3c or sts-1 data, and txd- updated on the falling edge of txc+/-. these outputs could be programmed to be pure pecl. default is a rail-to-rail swing. pin #: txd+/15, txd-/16 txprty transmit parity i indicates the parity of the tdat[7:0] bus. odd or even parity may be selected. txprty is sampled on the rising edge of tfclk and considered valid only when twrenb is asserted. txprty has an integral pull-down resistor. a maskable parity error is generated if an error is detected, but the cells with parity errors are not filtered. pin #: 95 txvcc power p power pin for txc+/- and txd+/- outputs. should be physically isolated from the other power analog pins and connected to a well coupled 5v dc source. pin #: 12 pin descriptions (continued)
8.03 8 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range absolute maximum ratings (1) symbol rating commercial unit v term terminal voltage C0.5 to +7.0 v with respect to dvgnd t a operating 0 to +70 c temperature t bias temperature under C55 to +125 c bias t stg storage C55 to +125 c temperature i out dc output current 50 ma note: 3139 tbl 02 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. symbol parameter conditions max. unit c in (1) input vin = 0v 10 pf capacitance c out (1) output vout = 0v 10 pf capacitance capacitance (ta = +25 c) note: 3139 tbl 05 1. characterized values, not currently tested. notes 1. all inputs operate at ttl levels except the pecl inputs. 2. rdat[7:0], rxprty, rcp, rgfc, rsoc, tca, tclk, rclk, tcp outputs have an 8 ma drive capability, while all other digital outputs have 4 ms drive. 3. all analog power/ground pins should be isolated from the digital power/ground pins, preferably with separate power supplies. it is recommanded to have separate ground planes on the board also. symbol name i/o description txgnd ground g ground pin for txc+/- and txd+/- outputs. should be physically isolated from the other ground analog pins. pin #: 17 vcc power p core and pad ring power connected to a decoupled 5v dc pin #: 18, 20, 55, 61, 73, 81, 107, 114 vclk vector clock i vclk is used as a test mode input to the chip. it should be asserted only when testing the chip on a tester. it shortens the count values for most receive error counters to enable the testing to be done in a reasonable amount of time. vclk has an intergral pull-down registor. pin #: 99 wr write i active low write signal to update registers. the data bus contents are latched into the addressed register on the rising edge of the write signal when the chip select (cs) is asserted. pin #: 104 xoff transmit off i transmit off signal prevents the insertion of cells from the transmit fifo into the transmit frames. if asserted, idle/unassigned cells only are transmitted irrespective of the state of the transmit fifo. xoff is an asynchronous signal and has an integral pull-down registor. pin #: 50 pin descriptions (continued)
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 9 desired desired denominator window bip calculated calculated ber detectiion multiple length threshold ber detectiopn trigger time trigger time 1e-3 0.008s 0 64 19 0.988e-3 0.008s 1e-4 0.013s 0 104 2 1.040e-4 0.013s 1e-5 0.100s 20 38 4 0.991e-5 0.0998s 1e-6 1.000s 989 8 19 0.998e-6 0.990s 1e-7 10.00s 7849 10 15 0.994e-7 9.810s 1e-8 83.00s 41615 16 7 0.875e-8 83.23s 1e-9 667.0s 52313 102 1 0.994e-9 666.99s table 1. b2 ber detection configuration table dc electrical characteristics symbol parameter min. typ. max. unit v cc digital supply voltage 4.5 5.0 5.5 v gnd digital ground voltage 0 0 0 v v ilp pecl input low voltage vcc-1.8v vcc-1.6v v v ihp pecl input high voltage vcc-1.0v vcc-0.8v v v olp pecl output low voltage vcc-1.8v vcc-1.6v v v ohp pecl outut high voltage vcc-1.0v vcc-0.8v v v il ttl input low voltage 0.8 v v ih ttl input high voltage 2.0 v v ol ttl output low voltage 0.4 v v oh ttl output high voltage 2.4 v av cc analog supply voltage 4.5 5.0 5.5 v agnd analog ground voltage 0 0 0 v i dd1 power supply current 85 (155.52mbps) ma 55 (51.84mbps) i dd2 average standby current 100 m a
8.03 10 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range functional description clock recovery the clock recovery block recovers the clock from the receiving serial data stream. this block can be selected to utilize reference clocks at 6.48 mhz or 19.44 mhz. this unit provides a status bit to indicate whether it is locked to data or the reference clock. the clock recovery unit also provides a loss of signal (los) input and a diagnostic loopback. the pll originally locks to the reference clock. the ppl will lock to the data when the frequency of the recovered clock is within 244 ppm of the reference clock. once in data lock, the pll switches to the reference clock if there is no data transition for an 80 bit period or the recovered clock drifts for over 244 ppm of the reference clock. the transmit clock could be derived from the recovered clock (loop timing) by configu- ration. serial to parallel this block performs the serial to parallel conversion of incoming bit serial data into byte serial data. receive sonet framer the receive sonet framer performs frame synchroniza- tion, descrambling, pointer interpretation, sonet section, line, and path overhead processing, alarm and performance monitoring functions. the framer determines the out-of-frame/in-frame status for the sts-3c/sts-1 data by checking the framing pattern (a1, a2). out-of-frame is declared when four consecutive frames with errored framing patterns are received. while out-of- frame, the framer searches for the correct framing pattern, in- frame is declared upon detecting two consecutive error-free framing patterns. the loss of frame (lof) status is determined by monitor- ing the out-of-frame/in-frame conditions. this block provides the 3 ms out-of-frame timer and in-frame timer. the in-frame timer accumulates when the out-of-frame is absent; it stops accumulating and is reset to zero when the out-of-frame is present. the out-of-frame timer accumulates when the out-of- frame is present; it stops accumulating when the out-of-frame is terminated. for the intermittent out-of-frame conditions, it is only reset to zero when the out-of-frame is absent continu- ously for 3 ms (i.e., the in-frame timer reaches 3 ms). the lof is declared when the accumulated out-of-frame timer reaches 3 ms. once detected, the lof defect is termi- nated when the in-frame timer reaches 3 ms. the loss of signal (los) block checks the incoming scrambled data availability. los is declared when 20 + 3 m s of all-zero pattern is detected. loss of signal is cleared when two consecutive valid framing patterns is detected, and during the intervening time (one frame), no all-zero pattern qualifying as los defect exits. the incoming data stream is descrambled. the scrambling polynomial is 1 + x 6 + x 7 and the sequence length is 127. the framing bytes (a1, a2) and the identity bytes (c1) are not descrambled. the descrambling function can be disable by a register control bit. the b1 ber is monitored by the incoming section bip-8 error detection code (b1). the bip-8 code is calculated over all bits of the complete sts-3c or sts-1 frame before descrambling by bit interleaved parity calculation using even parity. and obtains errors by comparing the calculated bip-8 code with the bip-8 code extracted from the b1 byte of the next incoming frame. up to 64,000 (8 x 8000) bit errors can be detected for one second. one 16-bit saturating counter is provided to accumulate these bip errors. this counter is to be read via microproces- sor interface at least once per second for performance moni- toring. the b2 ber is monitored by the incoming line bip-8/24 error detection code (b2). the bip-8/24 code is calculated over all bits of the line overhead and synchronous payload envelope after descrambling by bit interleaved parity calcula- tion using even parity. and obtains errors by comparing the calculated bip-8/24 code with the bip-8/24 code extracted from the b2 byte of the next incoming frame. up to 192,000 (24 x 8000) bit errors can be detected for one second. one 20-bit saturating counter is provided to accumulate these bip errors. this counter is to be read via microprocessor interface at least once per second for the performance monitoring. the defect detection for b2 eber is also provided. the receive b2 ber detection algorithm provides a method for detection of a preset bit error rate (ber) in the incoming sonet/sdh data stream. upon detection of the preset level, the IDT77155 can optionally assert its interrupt pin and provide status information. the algorithm provides two identical, programmable ber detection blocks that will allow the user to detect ber by setting two independent ber thresholds. this can be used to provide the warning and fail thresholds needed to comply with the sonet/sdh specification for automatic protection switching (aps). to detect the ber for warning and fail level. three configuration registers are provided respectively. denominator (dm) register: 16-bit register, number of frames (frames = dm + 1) that are used to compute the ber. window length (wl) register: 8-bit register, length of the sliding window in frames. bip threshold (bt) register: 8-bit register, value for the bip threshold. the denominator, window length, and bip threshold registers are configured according to table 1 for warning and fail ber detection respectively. the first two rows are fail levels, and the remaining are warning levels. the line alarm indication signal (ais) is detected in the incoming data stream. line ais is declared when five con- secutive frames 111 pattern in bits 6-8 of k2 byte are detected. line ais is removed when five consecutive frames
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 11 of any pattern other than 111 in bits 6-8 of k2 byte are detected. for sdh applications, line ais is declared when three consecutive frames 111 pattern in bits 6-8 of k2 byte are detected. line ais is removed when three consecutive frames of any pattern other than 111 in bits 6-8 of k2 byte are detected. the selection of sonet or sdh detection criteria is set by control register. the line remote defect indication (rdi) is detected in the incoming data stream. line rdi is declared when five con- secutive frames of 110 pattern in bits 6-8 of k2 byte are detected. line rdi is removed when five consecutive frames of any pattern other than 110 in bits 6-8 of k2 byte are detected. for sdh applications, line rdi is declared when three consecutive frames of 110 pattern in bits 6-8 of k2 byte are detected. line rdi is removed when three consecutive frames of any pattern other than 110 in bits 6-8 of k2 byte are detected. the selection of sonet or sdh detection criteria is set by control register. k1 and k2 bytes are extracted if new identical values are received for 3 consecutive frames for automatic switch protection (aps) use. the line far end block error (lfebe) can be monitored by extracting the 8-bit febe from the incoming third z2 byte. the error count range is from 0 to 24 errors. any other value is counted as zero error. up to 192,000 (24x 8000) bit errors can be detected for one second, one 20-bit saturating counter is provided to accumulate these febe errors. this counter is to be read and reset via microprocessor interface. the pointer interpreter interprets the incoming pointer byte (h1, h2) to determine the location of the j1 byte (path overhead) in the incoming sts-3c or sts-1 data stream. the pointer interpreter detects loss of pointer (lop) and path ais in the incoming sts-3c or sts-1 data stream. lop is declared when eight consecutive invalid pointers or eight consecutive ndf enabled indications are detected. lop is removed when three consecutive same valid pointers with normal ndf are detected. path ais is declared when three consecutive all-one pattern in h1 and h2 byte are detected. path ais is removed when three consecutive same valid pointers with normal ndf are detected or when a valid pointer with ndf enabled is detected. the b3 ber is monitored by the incoming path bip-8 error detection code (b3). the bip-8 code is calculated over all bits of the synchronous payload envelope after descrambling by bit interleaved parity calculation using even parity. and obtains errors by comparing the calculated bip- 8 code with the bip-8 code extracted from the b3 byte of the next incoming frame. up to 64,000 (8 x 8000) bit errors can be detected for one second. one 16-bit saturating counter is provided to accumulate these bip errors. this counter is to be read via microproces- sor interface at least once per second for performance moni- toring. c2 mismatch is detected in the incoming data stream. c2 mismatch is declared when five consecutive frames of the value other than 13h in c2 byte are detected. c2 mismatch is removed when five consecutive frames of the value 13h in c2 byte are detected. the path far end block error (pfebe) can be monitored by extracting the 4-bit febe from the incoming path status byte (g1). the error count range is from 0000 to 1000 to represent zero to eight errors. any other value is counted as zero error. up to 64,000 (8 x 8000) bit errors can be detected for one second, one 16-bit saturating counter is provided to accumulate these febe errors. this counter is to be read and reset via microprocessor interface. path remote defect indication (rdi-p) is detected by checking the bit 5 of path status byte (g1) in the incoming data stream. path rdi is declared when ten consecutive frames of value 1 in bit 5 of g1 byte are detected. path rdi is removed when ten consecutive frames of value 0 in bit 5 of g1 byte are detected. receive utopia cell fifo the receive utopia cell fifo provides functions for atm cell delineation, hec error verification, cell filtering, and atm cell payload descrambling. this block also provides a four cell deep receive fifo. cell delineation is for validating the hec of a cell header by checking with the crc-8 calculation over first 4 bytes of atm cell header; the coset value of 55h can be optionally added to the hec during validation. hec validation uses the state machine in ccitt recommendation i.432 and is shown in figure 1. the state machine shown in figure 1 is initialized to the hunt state in which every byte of atm 53 byte is checked for a valid hec. once correct hec has been found, cell delineation state machine enters the presync state that validates hec on a cell by cell basis. if additional delta (value is suggested to be six) consecutive correct hecs are validated, the state machine enters the sync state. how- ever, if any incorrect hec is found in the presync state, the state machine reverts to hunt state. once in sync state, it stays in the sync state until alpha (value is suggested to be seven) consecutive incorrect hecs are detected. hunt state is entered and the search for a correct hec on a byte by byte basis resumes. cell could be discarded with hec errors by using hec
8.03 12 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range verification while in sync state. the hec verification state machine is shown in figure 2. the state machine is initialized to correction mode. cells with no hec errors are passed to the receive fifo. any single bit error detected in the incoming cell headers are corrected and the cells are passed. it enters into detection mode if any single bit or multi-bit errors in the header are detected. in detection mode, all cells with single or multi-bit errors are dropped. only cells with no errors are passed. when a cell with no hec error is detected in detec- tion mode, it enters back to correction mode. however, if seven consecutive cells with errored hec are received, hunt state is entered from the detection mode. the atm descrambler descrambles the incoming 48 byte cell payload only (header is not descrambled) by using poly- nomial x 43 + 1. the descrambling function may be disabled. one 8-bit saturating hec correctable error counter, one 8- bit saturating hec uncorrectable error counter, and a 19-bit saturating receive cell counter are provided for atm cell performance monitoring . the hec correctable error counter accumulates hec single bit errors in the header. the hec uncorrectable error counter accumulates hec multiple bit errors in the header. the receive cell counter accumulates the number of assigned cells. all counters are active only in the sync state. these three counter are to be read via microprocessor interface at least once per second for performance monitor- ing. the received gfc bits are output in a serial stream via the gfc extraction output. gfc bits are extracted for every received cell with the rcp output to indicate the position of the most significant bit. the gfc output may be disabled via the control register or no cell delineation. the receive fifo has four atm cells depth. it provides fifo management and the separation of sts-3c or sts-1 timing from atm layer timing. the fifo management functions are to fill the receive four cells fifo and indicate when cells are ready to be read from the receive fifo and to detect fifo overflow and underflow. when overflow, the receive fifo discards the incoming atm cells, a maskable interrupt and status register also active for overflow condition. when underflow, the read is ignored. when fifo data is read out by rfclk, the start of cell (rsoc) is active. the cell available status (rca) is provided to indicate a cell is available in the receive fifo. clock synthesis the clock generator generates the 155.52 or 51.84 mhz transmit clock by locking to a 1/8-frequency reference clock i.e., synthesized from a 19.44 mhz or 6.48 mhz reference clock. parallel to serial this block performs the parallel to serial conversion to convert the outgoing byte serial data to bit serial data. transmit sonet framer the transmit sonet framer provides framing pattern (a1, a2) insertion, scrambling, pointer generation, sonet section, line and path overhead insertion, and alarm signal insertion. the framing pattern (a1, a2) and c1 are inserted into outgoing sts-3c or sts-1 data stream. the framing bit error may be insert for diagnostic. the sts scrambler scrambles the outgoing data except framing bytes (a1, a2) and identity byte (c1) by the using polynomial 1 + x 6 + x 7 . scrambling may be disabled via control register. an all-zero pattern may be inserted via micropro- cessor interface after scrambling for diagnostic information. the outgoing section bip-8 error detection code (b1) is calculated over all bits of the complete sts-3c or sts-1 frame after scrambling by bit interleaved parity calculation using even parity. the calculated bip-8 code is then inserted into the b1 byte of the next outgoing frame before scrambling. corrupted bip-8 code may be inserted via control register for diagnostic information. the line ais may be set for outgoing data stream by inserting all-one pattern into line overhead and synchro- nous payload envelope (spe) of sts-3c or sts-1 frame by control register via microprocessor interface. the line remote defect indication (rdi) may be set for outgoing data stream by inserting 110 pattern in bits 6-8 of k2 byte to generate line rdi. k1 and k2 byte may be inserted for outgoing data stream for automatic switch protection (aps) use. the outgoing line bip-8 error detection code (b2) is calcu- lated over all bits of the line overhead and synchronous payload envelope (spe) of sts-3c or sts-1 frame before scrambling by bit interleaved parity calculation using even parity. the calculated bip-8 code is then inserted to the b2 byte of the next outgoing frame before scrambling. corrupted bip-8 code may be inserted via control register for diagnostic information. the line febe can be inserted by accumulating detected b2 bip-8 errors from receive direction into febe code of the third z2 byte for transmit sts-3c frame. the pointer generator generates the pointer (h1, h2) for outgoing sts-3c or sts-1 data stream. the ss bits of pointer is programmable for the sdh requirement. the loca- tion of start of the synchronous payload envelope (spe) is according to the value of generated pointer.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 13 the outgoing path bip-8 error detection code (b3) is calculated over all bits of synchronous payload envelope (spe) of sts-3c or sts-1 frame before scrambling by bit interleaved parity calculation using even parity. the calcu- lated bip-8 code is then inserted to the b3 byte of the next outgoing frame before scrambling. corrupted bip-8 code may be inserted via control register for diagnostic. the c2 byte is set as 13h by default for atm mapping. value of c2 may be set by control register via microprocessor. the path febe can be inserted by accumulating detected b3 bip-8 errors from receive direction into febe code of the path status byte (g1) for transmit sts-3c or sts-1 frame. path febe may be inserted via control register for diagnostic information. the path remote defect indication (rdi) may be set for outgoing data stream by inserting 1 into bit 5 of path status byte (g1). h4 can be inserted by the value, which indicates the offset between h4 byte position and the atm cell boundary of the first cell at the same row. synchronous payload envelope (spe) can be mapped into outgoing sts-3c or sts-1 frame according to the gener- ating pointer. transmit utopia cell fifo the atm scrambler scrambles the out going 48 byte cell payload only (header is not scrambled) by using polynomial x 43 + 1. the scrambling function may be disabled. the idle cell generator block inserts idle/unassigned cells into the transmit cell stream if a complete atm cell was not written into the transmit fifo. the gfc, pti and clp may be set via control registers. the all-zero pattern is inserted into the vci/vpi of header. hec of the idle cell is calculated and inserted. the hec generator calculates the crc-8 code over the first four byte of header and inserts the crc-8 code into the fifth byte of header. the polynomial x 8 + x 2 + x + 1 for hec generation is used. the coset polynomial x 6 + x 4 + x 2 + 1 is added to the residue. a 19-bit saturating transmit cell counter is provided for atm cell performacne monitoring. the four serial gfc bits are inserted according to the framing pulse of the transmit cell. the value of gfc bits may be set by the control registers. the transmit fifo has four atm cells depth. it provides fifo management and the separation of sts-3c or sts-1 timing from atm layer timing. the fifo management functions are to fill the transmit four cells fifo and indicate when cells are ready to be written into the transmit fifo and to detect fifo overflow condition. when the transmit fifo contains four cells and the upstream device still writes cell into fifo, the overflow condition will be indicated. a maskable interrupt and status register also active for overflow condition. the write signal and all data writing into fifo are ignored until there is a space in fifo. microprocessor interface the microprocessor interface provides interface logic circuit and the registers for the functions of configuration, monitoring, control and test. figure 1. cell delineation state diagram
8.03 14 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range h2 p44 p45 p46 p47 p48 h1 tfclk tca tsoc tdat[0:7] txprty h1 tcalevel0 = 1 x x x 3497 drw 08 x figure 2. hec verification state diagram figure 3. transmit waveform for utopia interface h2 p44 p45 p46 p47 p48 h1 rfclk rca rsoc rdat[0:7] rxprty h1 rcalevel0 = 0 3497 drw 09 z x x figure 4. re-
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 15 tclk tgfc tcp gfc[3] gfc[2] gfc[1] gfc[0] xx 3497 drw 10 rclk rgfc rcp gfc[3] gfc[2] gfc[1] gfc[0] xx 3497 drw 11 figure 6. receive gfc serial link waveform figure 5. transmit gfc serial link waveform
8.03 16 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range operation modes multi-phy operation multiple IDT77155s may be connected to common bus when a multi-phy system architecture is needed. both transmit and receive utopia busses, as well as the utility bus, can attach to common busses. device selection is controlled via the utopia enable control signals ( twrenb, rrdenb) and multi-phy ad- dressing signals (txaddr[1:0], rxaddr[1:0]). in transmit, twrenb tells the selected device (selected by txaddr[1:0]) that the data and control signals it sees are to be used for atm cell transmission. in receive, when rrdenb is not asserted (active low), rdat[7:0], rxprty, rsoc, and rca are all tri- stated, allowing them to share a common bus. when rrdenb is asserted, the selected device (selected by rxaddr[1:0]) drives these outputs, transferring the data to the upstream hardware. ? loopback the IDT77155 supports two loopback functions that are enabled by control bits in the control register. ? local loopback the local loopback mode provides a connection within the phy between transmit and receive data. this loopback con- nects the high speed transmit data and clock to the high speed receive data and clock as shown in figure 9. note that while this mode is operating, no data is forwarded to or received from the line interface. ? line loopback the line loopback might also be called remote loopback since it provides for a means to test the overall system, including the line. the line loopback connects the high speed receive data and clock to the transmit data and clock as shown in figure 10. "upstream" hardware 77155#1 optical transceiver 77155#2 77155#3 77155#4 "utopia transmit bus" ?dat[7:0] ?xprty ?soc ?xaddr[1:0] 77155 drw 12 12 12 12 12 12 optical transceiver optical transceiver optical transceiver tca "upstream" hardware 77155#1 optical transceiver 77155#2 77155#3 77155#4 "utopia receive bus" ?dat[7:0] ?xprty ?soc ?xaddr[1:0] 77155 drw 13 12 12 12 12 12 optical transceiver optical transceiver optical transceiver rca figure 7. multi-phy: transmit direction figure 8. multi-phy: receive direction
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 17 figure 10. line loopback encoder parallel to serial transmit sonet framer clk gen. transmit atm cell fifo clk rec. serial to parallel receive sonet framer decoder receive utopia cell fifo encoder clk rec. rrclk+ rrclk- alos+ alos- rxd+ rxd- rxdo+ rxdo- rbyp rclk rgfc rca txaddr[1:0] trclk+ trclk- txd+ txd- txc+ txc- tbyp rate0 tclk tcp transmit utopia cell fifo mphyen apt1 lf lf+ lfo ralm rfp rcp atp2 rate1 tfpo xoff tgfc tca tsoc tdat[7:0] txprty tfclk rsoc rdat[7:0] rxprty rfclk tsen rxaddr[1:0] 3497 drw 07 micoprocessor interface d[7:0] a[7:0] ale encoder parallel to serial transmit sonet framer clk gen. transmit atm cell fifo clk rec. serial to parallel receive sonet framer decoder receive utopia cell fifo encoder clk rec. rrclk+ rrclk- alos+ alos- rxd+ rxd- rxdo+ rxdo- rbyp rclk rgfc rca txaddr[1:0] trclk+ trclk- txd+ txd- txc+ txc- tbyp rate0 tclk tcp transmit utopia cell fifo mphyen apt1 lf lf+ lfo ralm rfp rcp atp2 rate1 tfpo xoff tgfc tca tsoc tdat[7:0] txprty tfclk rsoc rdat[7:0] rxprty rfclk tsen rxaddr[1:0] 3497 drw 06 micoprocessor interface d[7:0] a[7:0] ale rst figure 9. local loopback
8.03 18 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range register listing address register 0x00 master reset & id register 0x01 configuration register 0x02 interrupt register 0x04 master clock monitor register 0x05 master control register 0x06 transmit clock synthesis control/status register 0x07 receive clock/data recovery control/stuts register 0x10 receive section overhead control register 0x11 receive section overhead status register 0x12 receive section bip error counter (lsb) 0x13 receive section bip error counter (msb) 0x14 transmit section overhead control register 0x15 transmit section overhead control register 0x18 receive line overhead status register 0x19 receive line overhead interrupt register 0x1a receive line bip error counter (lsb) 0x1b receive line bip error counter 0x1c receive line bip error counter (msb) 0x1d receive line febe counter (lsb) 0x1e receive line febe counter 0x1f receive line febe counter (msb) 0x20 transmit line overhead stutus register 0x21 transmit line overhead control register 0x24 transmit k1 byte register 0x25 transmit k2 byte register 0x26 receive k1 byte register 0x27 receive k2 byte register 0x30 receive path overhead status register 0x31 receive path overhead interrupt register 0x33 receive path overhead interrupt enable register 0x37 receive path signal lable byte register 0x38 receive path bip error counter (lsb) 0x39 receive path bip error counter (msb) 0x3a receive path febe counter (lsb) 0x3b receive path febe counter (msb) 0x3d receive path bip error control register address register 0x40 transmit path overhead control register 0x41 tramsmit pointer control register 0x45 transmit pointer lsb register 0x46 transmit pointer msb register 0x48 transmit path signal lable byte register 0x49 transmit path overhead control register 0x50 receive cell control register 0x51 receive cell interrupts & interrupt enable register 0x52 receive cell match header register 0x53 receive cell match header mask register 0x54 receive cell correctable error counter 0x55 receive cell uncorrectable error counter 0x56 receive cell counter (lsb) 0x57 receive cell counter 0x58 receive cell counter (msb) 0x59 receive cell configuration register 0x5a receive id address register 0x60 transmit cell control register 0x61 transmit cell idle/unassigned cell header pattern 0x62 transmit cell idle/unassigned cell header pattern 0x63 transmit cell configuration register 0x64 transmit cell counter (lsb) 0x65 transmit cell counter 0x66 transmit cell counter (msb) 0x67 transmit cell configuration register 0x68 transmit id address register 0x70 receive ber status/control register 0x71 receive ber fail threshold register 0x72 receive ber fail window register 0x73 receive ber fail denominator register (lsb) 0x74 receive ber fail denominator register (msb) 0x75 receive ber warning threshold register 0x76 receive ber warning window register 0x77 receive ber warning denominator register (lsb) 0x78 receive ber warning denominator register (msb) 0x7f output pecl control register
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 19 configuration, control and status registers master reset & id register default = 8b00110000 address 0x00 bit type symbol function bit 7 r/w mstreset software reset control. a logic one resets entire sonet digital logic, and a logic zero has to be written to clear software reset. it resets the whole chip into a low-power stand-by mode. a hardware reset sets the whole register to its default state. bit 6 r type[2] type value for the identification of chip. bit 5 r type[1] type value for the identification of chip. bit 4 r type[0] type value for the identification of chip. bit 3 r id[3] revision id number. bit 2 r id[2] revision id number. bit 1 r id[1] revision id number. bit 0 r id[0] revision id number. configuration register default = 8b01110000 address 0x01 bit type symbol function bit 7 reserved bit 6 r/w autofebe controls assertion of far end block errors (febe) in the transmit stream upon detection of line and path error events. when set to logic one, path febe errors are inserted in the transmit stream for each line or path bip error event in the receive stream. when deasserted, no such errors are inserted. bit 5 r/w autolrdi controls assertion of line remote defect indication (lrdi) upon detection of alarms. when set to a logic one, a line rdi is inserted into the transmit stream upon detection of los, lof, or lais in the receive stream. bit 4 r/w autoprdi controls assertion of path remote defect indication (prdi) upon detection of alarms. when set to a logic one, prdi is inserted into the transmit stream upon detection of an los, lof, lais, lop, pais, or loc signal. bit 3 r/w tcainv select active polarity of tca signal. default is the tca signal being active high. bit 2 r/w rcainv select active polarity of rca signal. default is the rca signal being active high. bit 1 r/w rxdinv select active polarity of the rxd+/- inputs. default selects rxd+ to be active high and rxd- to be active low. bit 0 reserved
8.03 20 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range interrupt register default = 8bxxxxxxxx address 0x02 bit type symbol function bit 7 r txoolint transmit reference out of lock interrupt status indication. it indicates the transmit clock synthesis pll is unable to lock to the reference frequency trclk+/-. this bit is cleared when the register is read. bit 6 r rxlocint asserted when the loss of cell delineation (loc) signal changes state. this bit is reset after a read to this register. bit 5 r rxoolint receive data out of lock interrupt status indication. it indicates the receive clock/data recovery plls recovered clock is not within bellcores requirement of frequency variation with respect to the reference clock rrclk+/-. it is also asserted if no transitions have occurred on the rxd+/- inputs for 80 bit periods. this bit is cleared when the register is read. bit 4 r txcdi interrupt is asserted upon the detection of an interrupt from the tx cell delineation block. bit 3 r rxcdi interrupt is asserted upon the detection of an interrupt from the rx cell delineation block. bit 2 r rxpohi interrupt is asserted upon the detection of an interrupt from the rx path overhead section of the transmission convergence block. bit 1 r rxlohi interrupt is asserted upon the detection of an interrupt from the rx line overhead section of the transmission convergence block. bit 0 r rxsohi interrupt is asserted upon the detection of an interrupt from the rx section overhead section of the transmission convergence block. master clock monitor register default = 8bxxxxxxxx address 0x04 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r rrclkreg rrclk+/- monitor. set on the rising edge of rrclk+/-. cleared when this register is read. bit 2 r trclkreg trclk+/- monitor. set on the rising edge of trclk+/-. cleared when this register is read. bit 1 r rclkreg rclk monitor. set on the rising edge of the output clock rclk. cleared when this register is read. bit 0 r tclkreg tclk monitor. set on the rising edge of the output clock tclk. cleared when this register is read.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 21 master control register default = 8b00100000 address 0x05 bit type symbol function bit 7 r/w rxlocien loss of cell delineation interrupt enable. when set to a logic one, the intb signal of the chip is asserted when a change in the loc signal occurs. bit 6 r loc loss of cell delineation (loc) indication. bit 5 r/w txfixptr set payload pointer at 522 and disable any pointer movement. (default = 1) bit 4 reserved bit 3 reserved bit 2 r/w txlloop line loopback enable. when a logic one, txd+/- are connected internally to rxd+/-. bit 1 r/w rxdloop diagnostic loopback enable. the serial output and clock streams are connected internally to the serial input streams. bit 0 r/w rxloopt loop time operation enable. when a logic one, the transmitter clock is the recovered receive clock when rbyp is disabled, or rrclk+/- when rbyp is asserted. by default, the transmit clock is derived from trclk+/-. transmit clock synthesis control/status register default = 8b0000x000 address 0x06 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r txool transmit out of lock status signal indicating the transmit clock synthesis logic is unable to lock to the reference clock trclk+/-. bit 2 reserved bit 1 r/w txoolien interrupt enable for the transmit out of lock indication. bit 0 r/w txrefsel selects the expected frequency of trclk+/-. if a logic 0, the reference frequency is 19.44 mhz, else the reference frequency must be 6.48 mhz. it affects the clock synthesis frequency only when tbyp is deasserted. receive clock/data recovery control/status register default = 8b0000x000 address 0x07 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r rxool receive out of lock status signal indicating the receive clock/data recovery logic is unable to lock to the input data stream. it is asserted if the recovered clock is not within 244ppm of the reference clock rrclk+/- or if there are no transitions on the rxd+/- inputs for 80n bit periods. bit 2 reserved bit 1 r/w rxoolien interrupt enable for the receive out of lock indication. bit 0 r/w rxrefsel selects the expected frequency of rrclk+/-. if a logic 0, the reference frequency is 19.44 mhz, else the reference frequency must be 6.48 mhz. it affects the clock/data recovery logic frequency only when rbyp is deasserted.
8.03 22 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range receive section overhead control register default = 8b00000000 address 0x10 bit type symbol function bit 7 reserved bit 6 r/w scrdis disable receive frame scrambler if set to logic one. bit 5 w frcoof when set to logic one, the receive section overhead logic is forced out of frame at the next frame boundary. bit 4 reserved bit 3 r/w b1errien interrupt enable for rx section bip (b1) error. when asserted, an interrupt is generated if section bip (b1) error is detected. bit 2 r/w losien receive loss of signal interrupt enable. when asserted, an interrupt is generated if los alarm changes state. bit 1 r/w lofien receive loss of frame interrupt enable. when set to logic one, an interrupt is generated if lof alarm changes state. bit 0 r/w oofien receive out of frame interrupt enable. when set to logic one, an interrupt is generated if oof alarm changes state. receive section overhead status register default = 8bxxxxxxxx address 0x11 bit type symbol function bit 7 r c1int interrupt bit set if received c1 bytes received do not correspond to 1, 2, 3 respectively. this bit is cleared when this register is read. bit 6 r b1errint interrupt is asserted if section bip (b1) errors received. this bit is cleared when this register is read. bit 5 r losint loss of signal interrupt is asserted if los changes state. this bit is cleared when this register is read. bit 4 r lofint loss of frame interrupt is asserted if lof changes state. this bit is cleared when this register is read. bit 3 r oofint out of frame interrupt is asserted if oof changes state. this bit is cleared when this register is read. bit 2 r los loss of signal status indication. asserted high. bit 1 r lof loss of frame status indication. asserted high. bit 0 r oof out of frame status indication. asserted high. receive section bip error counter default = 16hxxxx address 0x12 bit type symbol function bit 7 r b1errcnt[7] b1 error counter bit bit 6 r b1errcnt[6] b1 error counter bit bit 5 r b1errcnt[5] b1 error counter bit bit 4 r b1errcnt[4] b1 error counter bit bit 3 r b1errcnt[3] b1 error counter bit bit 2 r b1errcnt[2] b1 error counter bit bit 1 r b1errcnt[1] b1 error counter bit bit 0 r b1errcnt[0] b1 error counter bit
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 23 address 0x13 bit type symbol function bit 7 r b1errcnt[15] b1 error counter bit bit 6 r b1errcnt[14] b1 error counter bit bit 5 r b1errcnt[13] b1 error counter bit bit 4 r b1errcnt[12] b1 error counter bit bit 3 r b1errcnt[11] b1 error counter bit bit 2 r b1errcnt[10] b1 error counter bit bit 1 r b1errcnt[9] b1 error counter bit bit 0 r b1errcnt[8] b1 error counter bit note: 1. b1errcnt[15:0] receive section overhead bip (b1) error counter. cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either register or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00. transmit section overhead control register default = 8b00000000 address 0x14 bit type symbol function bit 7 reserved bit 6 r/w scrdis disable transmit frame scrambler. scrambling enabled if logic zero. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 r/w laisins insert line alarm signal (lais) in transmit stream. line alarm results in all bits except the section overhead bytes being set to logic 1 prior to scrambling. transmit section overhead control register default = 8b00000000 address 0x15 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 r/w losins insert loss of signal into transmit stream. the transmit stream is forced to all zeroes if this bit is asserted. bit 1 r/w b1inv invert b1 byte before insertion into transmit stream. controls error insertion into the section b1 byte. bit 0 r/w frerrins insert framing error. inserts a single bit error continuously into the most significant bit of the a1 section overhead byte. when this bit is set to logic one, the a1 bytes transmitted are 0x76 instead of 0xf6.
8.03 24 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range receive line overhead status register default = 8b00000000 address 0x18 bit type symbol function bit 7 r/w b2word controls accumulation of b2 errors. if set to logic one, the b2 error counter is incremented only once per frame for one or more errors received during that frame. when disabled, the b2 error counter is incremented by the received error count during that frame. max b2 errors is 8 per frame for sts-1 and 24 for sts-3c per frame. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 r lais receive line alarm signal status indication. bit 0 r lrdi receive line remote defect indication status indication. receive line overhead interrupt register default = 8b0000xxxx address 0x19 bit type symbol function bit 7 r/w lfebeien receive line febe (z2) error interrupt enable. if set to logic one, an interrupt is generated if a line febe is detected. bit 6 r/w b2errien receive line bip (b2) error interrupt enable. if set to logic one, an interrupt is generated if a line bip (b2) error is detected. bit 5 r/w laisien receive line alarm indication signal interrupt enable. if set to logic one, an interrupt is generated if lais changes state. bit 4 r/w lrdiien receive line rdi error interrupt enable. if set to logic one, an interrupt is generated if line rdi signal changes state. bit 3 r lfebeint receive line febe (z2) error interrupt is asserted when a line febe is detected. cleared when this register is read. bit 2 r b2errint receive line bip error interrupt is asserted when a b2 error is detected. cleared when this register is read. bit 1 r laisint receive line alarm interrupt is asserted when a change in the line alarm signal (lais) occurs. cleared when this register is read. bit 0 r lrdiint receive line rdi interrupt is asserted when a change in the line rdi signal occurs. cleared when this register is read. receive line overhead bip error counter default = 20hxxxxx address 0x1a bit type symbol function bit 7 r b2errcnt[7] b2 error counter bit bit 6 r b2errcnt[6] b2 error counter bit bit 5 r b2errcnt[5] b2 error counter bit bit 4 r b2errcnt[4] b2 error counter bit bit 3 r b2errcnt[3] b2 error counter bit bit 2 r b2errcnt[2] b2 error counter bit bit 1 r b2errcnt[1] b2 error counter bit bit 0 r b2errcnt[0] b2 error counter bit
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 25 address 0x1b bit type symbol function bit 7 r b2errcnt[15] b2 error counter bit bit 6 r b2errcnt[14] b2 error counter bit bit 5 r b2errcnt[13] b2 error counter bit bit 4 r b2errcnt[12] b2 error counter bit bit 3 r b2errcnt[11] b2 error counter bit bit 2 r b2errcnt[10] b2 error counter bit bit 1 r b2errcnt[9] b2 error counter bit bit 0 r b2errcnt[8] b2 error counter bit address 0x1c bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r b2errcnt[19] b2 error counter bit bit 2 r b2errcnt[18] b2 error counter bit bit 1 r b2errcnt[17] b2 error counter bit bit 0 r b2errcnt[16] b2 error counter bit note: 1. b2errcnt[19:0] bip error counter of the receive line overhead section (b2 errors). cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the registers, or either of the z2 error registers, or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00. receive line febe counter default = 20hxxxxx address 0x1d bit type symbol function bit 7 r febecnt[7] febe counter bit bit 6 r febecnt[6] febe counter bit bit 5 r febecnt[5] febe counter bit bit 4 r febecnt[4] febe counter bit bit 3 r febecnt[3] febe counter bit bit 2 r febecnt[2] febe counter bit bit 1 r febecnt[1] febe counter bit bit 0 r febecnt[0] febe counter bit address 0x1e bit type symbol function bit 7 r febecnt[15] febe counter bit bit 6 r febecnt[14] febe counter bit bit 5 r febecnt[13] febe counter bit bit 4 r febecnt[12] febe counter bit bit 3 r febecnt[11] febe counter bit bit 2 r febecnt[10] febe counter bit bit 1 r febecnt[9] febe counter bit bit 0 r febecnt[8] febe counter bit address 0x1f bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r febecnt[19] febe counter bit bit 2 r febecnt[18] febe counter bit bit 1 r febecnt[17] febe counter bit bit 0 r febecnt[16] febe counter bit note: 1. febecnt[19:0] febe (far end block error in receive z2) counter of the receive line overhead section. cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the registers, or either of the b2 error registers, or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00
8.03 26 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range transmit k2 byte register default = 8b00000000 address 0x25 bit type symbol function bit 7 r/w k2ins[7] k2 insertion bit 7 bit 6 r/w k2ins[5] k2 insertion bit 5 bit 4 r/w k2ins[4] k2 insertion bit 4 bit 3 r/w k2ins[3] k2 insertion bit 3 bit 2 r/w k2ins[2] k2 insertion bit 2 bit 1 r/w k2ins[1] k2 insertion bit 1 bit 0 r/w k2ins[0] k2 insertion bit 0 note: 1. k2ins[7:0] value to be inserted into the k2 byte of transmit stream. continuously inserts this value into the transmit stream. however, the least significant 4 bits of the k2 byte in the transmit stream is overridden by the path rdi value and the line ferf value if error conditions are detected in the receive section of the transmission convergence logic. receive k1 byte register default = 8bxxxxxxxx address 0x26 bit type symbol function bit 7 r k1[7] receive k1 bit 7 bit 6 r k1[6] receive k1 bit 6 bit 5 r k1[5] receive k1 bit 5 bit 4 r k1[4] receive k1 bit 4 bit 3 r k1[3] receive k1 bit 3 bit 2 r k1[2] receive k1 bit 2 bit 1 r k1[1] receive k1 bit 1 bit 0 r k1[0] receive k1 bit 0 note: 1. k1[7:0] k1 byte of receive stream. updated if new k1 byte received for 3 consecutive frames. receive k2 byte register default = 8bxxxxxxxx address 0x27 bit type symbol function bit 7 r k2[7] receive k2 bit 7 bit 6 r k2[6] receive k2 bit 6 bit 5 r k2[5] receive k2 bit 5 bit 4 r k2[4] receive k2 bit 4 bit 3 r k2[3] receive k2 bit 3 bit 2 r k2[2] receive k2 bit 2 bit 1 r k2[1] receive k2 bit 1 bit 0 r k2[0] receive k2 bit 0 note: 1. k2[7:0] k2 byte of receive stream. updated if new k2 byte received for 3 consecutive frames transmit line overhead status register default = 8b00000000 address 0x20 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 r/w lrdi transmit line rdi insertion into transmit stream. when set to logic one, line rdi is inserted by transmitting the code 110 into the 3 least significant bits of the k2 byte of the transmit stream. transmit line overhead control register default = 8b00000000 address 0x21 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 r/w b2inv when set to logic one, b2 byte is inverted before insertion into transmit stream. transmit k1 byte register default = 8b00000000 address 0x24 bit type symbol function bit 7 r/w k1ins[7] k1 insertion bit 7 bit 6 r/w k1ins[6] k1 insertion bit 6 bit 5 r/w k1ins[5] k1 insertion bit 5 bit 4 r/w k1ins[4] k1 insertion bit 4 bit 3 r/w k1ins[3] k1 insertion bit 3 bit 2 r/w k1ins[2] k1 insertion bit 2 bit 1 r/w k1ins[1] k1 insertion bit 1 bit 0 r/w k1ins[0] k1 insertion bit 0 note: 1. k1ins[7:0] value to be inserted into the k1 byte of transmit stream. continuously inserts this value into the transmit stream.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 27 receive path overhead status register default = 8b00x0xx00 address 0x30 bit type symbol function bit 7 reserved bit 6 reserved bit 5 r lop receive loss of pointer (lop) status indication. bit 4 reserved bit 3 r pais receive path alarm indication (pais) status signal. bit 2 r prdi receive path remote path indication status indication. bit 1 reserved bit 0 reserved receive path overhead interrupt register default = 8bx0x0xxxx address 0x31 bit type symbol function bit 7 r c2int c2 label bytes error interrupt. asserted when the expected c2 value is not received for 5 consecutive frames. the c2byte register (h37) stores the most recently received c2 byte. bit 6 reserved bit 5 r lopint loss of pointer interrupt et when a change in lop signal occurs. cleared when this register is read. bit 4 reserved bit 3 r paisint path alarm indication signal interrupt is asserted when a change in the pais signal occurs. cleared when this register is read. bit 2 r prdiint path rdi interrupt is asserted when a change in the path rdi signal occurs. cleared when this register is read. bit 1 r b3errint path bip (b3) error interrupt is asserted when a path bip (b3) error is detected. cleared when this register is read. bit 0 r pfebeint path febe (bit 1-4 of g1) interrupt is asserted when a path febe is detected. cleared when this register is read. receive path overhead interrupt enable register default = 8b00000000 address 0x33 bit type symbol function bit 7 r/w c2ien c2 signal label bytes error interrupt enable if set to logic one, an interrupt is generated if a c2 error is detected. c2 error occurs when unexpected c2 bytes are received for 5 consecutive frames. bit 6 reserved bit 5 r/w lopien loss of pointer interrupt enable. if set to logic one, an interrupt is generated if a lop change is detected. bit 4 reserved bit3 r/w paisien path alarm indication signal interrupt enable. if set to logic one, an interrupt is generated if a pais change is detected. bit 2 r/w prdiien path rdi interrupt enable. if set to logic one, an interrupt is generated if a path rdi change is detected. bit 1 r/w b3errien path bip (b3) error interrupt enable. if set to logic one, an interrupt is generated if a path bip (b3) error is detected. bit 0 r/w pfebeien path febe (bit 1-4 of g1) interrupt enable. if set to logic one, an interrupt is generated if a path febe is detected.
8.03 28 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range receive path signal label byte register default = 8bxxxxxxxx address 0x37 bit type symbol function bit 7 r c2rx[7] receive c2 bit 7 bit 6 r c2rx[6] receive c2 bit 6 bit 5 r c2rx[5] receive c2 bit 5 bit 4 r c2rx[4] receive c2 bit 4 bit 3 r c2rx[3] receive c2 bit 3 bit 2 r c2rx[2] receive c2 bit 2 bit 1 r c2rx[1] receive c2 bit 1 bit 0 r c2rx[0] receive c2 bit 0 note: 1. c2rx[7:0] most recent errored path label byte received which led to the c2 interrupt. receive path overhead bip error counter default = 16hxxxx address 0x38 bit type symbol function bit 7 r b3errcnt[7] b3 error counter bit bit 6 r b3errcnt[5] b3 error counter bit bit 4 r b3errcnt[4] b3 error counter bit bit 3 r b3errcnt[3] b3 error counter bit bit 2 r b3errcnt[2] b3 error counter bit bit 1 r b3errcnt[1] b3 error counter bit bit 0 r b3errcnt[0] b3 error counter bit address 0x39 bit type symbol function bit 7 r b3errcnt[15] b3 error counter bit bit 6 r b3errcnt[14] b3 error counter bit bit 5 r b3errcnt[13] b3 error counter bit bit 4 r b3errcnt[12] b3 error counter bit bit 3 r b3errcnt[11] b3 error counter bit bit 2 r b3errcnt[10] b3 error counter bit bit 1 r b3errcnt[9] b3 error counter bit bit 0 r b3errcnt[8] b3 error counter bit note: 1. b3errcnt receive path overhead bip (b3) error counter. cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the registers, or either of the rdi error registers, or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00 receive path febe counter default = 16hxxxx address 0x3a bit type symbol function bit 7 r pfebecnt[7] path febe counter bit bit 6 r pfebecnt[5] path febe counter bit bit 4 r pfebecnt[4] path febe counter bit bit 3 r pfebecnt[3] path febe counter bit bit 2 r pfebecnt[2] path febe counter bit bit 1 r pfebecnt[1] path febe counter bit bit 0 r pfebecnt[0] path febe counter bit address 0x3b bit type symbol function bit 7 r pfebecnt[15] path febe counter bit bit 6 r pfebecnt[14] path febe counter bit bit 5 r pfebecnt[13] path febe counter bit bit 4 r pfebecnt[12] path febe counter bit bit 3 r pfebecnt[11] path febe counter bit bit 2 r pfebecnt[10] path febe counter bit bit 1 r pfebecnt[9] path febe counter bit bit 0 r pfebecnt[8] path febe counter bit note: 1. pfebecnt[15:0] receive path febe (bit 1-4 of g1 byte) counter. cumu- lative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the registers, or either of the bip (b3) error registers, or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master registerh00.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 29 receive path bip error control register default = 8b00000000 address 0x3d bit type symbol function bit 7 reserved bit 6 reserved bit 5 r/w blkbip controls accumulation of b3 errors. if set to logic one, the b3 error counter is incremented only once per spe for one or more errors received during that frame. when disabled, the b3 error counter is incremented by the received error count during that spe. max b3 errors is 8 per spe. bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 reserved transmit path overhead control register default = 8b00000000 address 0x40 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 r/w b3inv invert b3 byte before insertion into the transmission stream. when set to a logic one, the b3 byte is inverted causing the insertion of 8 bip errors per frame. the b3 byte is uncorrupted when this bit is a logic zero. bit 0 r/w paisins insert path alarm indication signal into the transmit stream. when a logic one, the complete spe, and the pointer bytes (h1, h2, & h3) are overwritten with the all ones pattern.
8.03 30 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range transmit pointer control register default = 8b00000000 address 0x41 bit type symbol function bit 7 reserved bit 6 r/w frcptr force the insertion of the pointer values (h1 & h2 bytes) in the pointer registers (h45, h46) into the transmit stream for diagnostics. the spe and other overheads are transmitted in a normal fashion although it would not be extracted by the receiving logic due to an incorrect pointer. at least one corrupted pointer is guaranteed to be sent. bit 5 r/w stuffctl stuff opportunity spacing between consecutive spe stuff events. when asserted to a logic one, stuff events controlled by incptr and decptr is generated at a maximum rate of once every four frames. else, stuff events may be generated every frame. bit 4 r/w ptr initialize pointer value of next frame with pointer value contained in h45 and h46. the registers at h45 and h46 are initialized before this bit is set to a logic one. if a legal pointer value is loaded (0 <= pointer <= 782) then the transmit pointer value is changed to this value with the spe being modified to this position appropriately. this bit is cleared once the new pointer is loaded. bit 3 r/w ndf controls insertion of the new data flags in h46 into the transmit stream. when asserted to a logic one, the pattern in h46 is inserted continuously in the payload pointer. when disabled, the normal pointer value (b0110) is inserted. bit 2 r/w decptr decrement pointer in the next immediate frame. this bit is cleared when the new pointer value is inserted in the transmit stream. this bit has no effect if the transmit fixptr bit is asserted. bit 1 r/w incptr increment pointer in the next immediate stream. this bit is cleared when the new pointer value is inserted in the transmit stream. this bit has no effect if the transmit fixptr bit is asserted. bit 7 reserved transmit pointer lsb register default = 8b00000000 address 0x45 bit type symbol function bit 7 r/w arbptr[7] arbitrary pointer bit 7 bit 6 r arbptr[6] arbitrary pointer bit 6 bit 5 r arbptr[5] arbitrary pointer bit 5 bit 4 r arbptr[4] arbitrary pointer bit 4 bit 3 r arbptr[3] arbitrary pointer bit 3 bit 2 r arbptr[2] arbitrary pointer bit 2 bit 1 r arbptr1] arbitrary pointer bit 1 bit 0 r arbptr[0] arbitrary pointer bit 0 note: 1. arbptr[7:0] payload pointer to be inserted into frame if ptr is set. a legal value results in the transmit payload pointer changing to the correspond- ing byte position. if the frcptr bit is set, the payload pointer changes to this arbitrary value but the spe position remains unchanged.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 31 transmit pointer msb register default = 8b10010000 address 0x46 bit type symbol function bit 7 r/w ndfval[3] new data flag field value to be inserted into the transmit stream if ldptr is set or if ndf bit is set. bit 6 r/w ndfval[2] bit 5 r/w ndfval[1] bit 4 r/w ndfval[0] bit 3 r/w ssbit[1] sonet/sdh switch bit and ss bits value of the transmit stream. if ssbit[1] is a logic high, then the chip transforms to full sdh mode. by default (ssbit[1] = 0), the chip follows the sonet specifications. sonet mode: ssbit[1] = 0 (1) ss bits of pointer is set to 00 for transmit direction. (2) line ais detection criteria. ais-l enter state: 5 consecutive frames with 111 in bits 6-8 of k2 byte are detected. ais-l exit state: 5 consecutive frames with pattern other than 111 in bits 6-8 of k2 byte are detected. (3) line rdi detection criteria. rdi-l enter state: 5 consecutive frames with 110 in bits 6-8 of k2 byte are detected. rdi-l exit state: 5 consecutive frames with pattern other than 110 in bits 6-8 of k2 byte are detected. (4) path bip-8 calculation for sts-1 applications count 87 columns of spe including 2 fixed stuffs column (column 30 and 59). (5) no consequent actions line rdi for transmit direction by detection of b2 eber (refer to register address h70 berfail) sdh mode: ssbit[1] = 1 (1) ss bits of pointer is set to 10 for transmit direction. (2) line ais detection criteria. ais-l enter state: 3 consecutive frames with 111 in bits 6-8 of k2 byte are detected. ais-l exit state: 3 consecutive frames with pattern other than 111 in bits 6-8 of k2 byte are detected. (3) line rdi detection criteria. rdi-l enter state: 3 consecutive frames with 110 in bits 6-8 of k2 byte are detected. rdi-l exit state: 3 consecutive frames with pattern other than 110 in bits 6-8 of k2 byte are detected. (4) path bip-8 calculation for sts-1 applications count 85 columns of spe excluding 2 fixed stuffs column (column 30 and 59). (5) generate consequent actions line rdi for transmit direction by detection of b2 eber (refer to register address h70 berfail) bit 2 r/w ssbit[0] ss bits value of the transmit stream. ssbit[0] is set to 0. bit 1 r/w arbptr[9] most significant bits of the arbitrary payload pointer to be inserted into frame if ldptr is set. a legal value results in the transmit payload pointer changing to the corresponding byte position. if the frcptr bit is set, the payload pointer changes to this arbitrary value but the spe position remains unchanged. bit 0 r/w arbptr[8]
8.03 32 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range transmit path signal lable byte register default = 8b00010011 address 0x48 bit type symbol function bit 7 r/w c2tr[7] transmit c2 bit 7 bit 6 r/w c2tr[6] transmit c2 bit 6 bit 5 r/w c2tr[5] transmit c2 bit 5 bit 4 r/w c2tr[4] transmit c2 bit 4 bit 3 r/w c2tr[3] transmit c2 bit 3 bit 2 r/w c2tr[2] transmit c2 bit 2 bit 1 r/w c2tr[1] transmit c2 bit 1 bit 0 r/w c2tr[0] transmit c2 bit 0 note: 1. c2tr[7:0]c2 value to be inserted into the transmit stream. default value is h13 for atm applications. value may be changed for diagnostics purposes. transmit path overhead control register default = 8b00000000 address 0x49 bit type symbol function bit 7 r/w pfebeins[3] insert febe value into path status byte. this value is cleared after it has been inserted into the path status byte for transmission. any non-zero value overrides the accumulated error values during the previous received frame. if a non-zero value is read from this register, it implies that the transmission is still pending. bit 6 r/w pfebeins[2] bit 5 r/w pfebeins[1] bit 4 r/w pfebeins[0] bit 3 r/w prdiins insert path remote defect indication into transmit stream. when set to a logic one, the prdi bit in the status byte is asserted. once a prdi indication is sent, it is guaranteed to be sent asserted for 10 consecutive frames. bit 2 r/w g1ins[2] g1 bits to be inserted into path status byte least significant bits. bit 2 r/w g1ins[1] bit 2 r/w g1ins[0]
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 33 receive cell control register default = 8b00000100 address 0x50 bit type symbol function bit 7 r ocd out of cell delineation status indication. when asserted high, the cell delineation state machine is in the hunt or presync state. bit 6 r/w parity select odd or even parity for rxprty output. when set to logic one, it is even parity over the outputs rdat[7:0], else it is odd parity. bit 5 r/w pass when enabled, filtering of cells with matching the pattern in cell header register h52 masked with the mask register h53 is disabled. filtering of field with vpi = vci = 0 is ignored and all cells are passed to the atm layer. bit 4 r/w cordis disables the hec error correction algorithm. any error detected in the incoming cell is treated as an uncorrectable error, and the cell is dropped. bit 3 r/w hecdis controls the dropping of cells when an incorrectable hec error is detected. when disabled, cells with uncorrectable errors are dropped. however, when set to a logic one, cells are passed to the tm layer regardless of the errors detected. the hec verification state machine is always in the correction mode. cells are always dropped when the cell delineation state machine is in the hunt or presync states. bit 2 r/w csetadd controls the addition of the coset polynomial. when a logic one, the coset polynomial is added to the header prior to comparison. bit 1 r/w scrdis controls the descrambling of the cell payload. when asserted high, payload scrambling is disabled. bit 0 r/w rxfiforst reset rx fifo. used to reset the four cell receive fifo when asserted to a logic one.the fifo ignores all writes until this bit is cleared. receive cell interrupts & interrupt enable register default = 8b000xxxx0 address 0x51 bit type symbol function bit 7 r/w ocdien out of cell delineation interrupt enable. if set to logic one, an interrupt is generated if an ocd change is detected bit 6 r/w hecien correctable or incorrectable hec error interrupt enable. if set to logic one, an interrupt is generated if a correctable or uncorrectable error is detected bit 5 r/w ovfien fifo overflow interrupt enable. if set to logic one, an interrupt is generated if a fifo overrun is detected bit 4 r ocdint out of cell delineation interrupt. set when the ocd signal changes value. this bit is cleared following a read to this register. bit 3 r corint correctable hec error interrupt is asserted when a correctable hec error is detected. this bit is cleared following a read to this register. bit 2 r uncorint uncorrectable hec error interrupt is asserted when an uncorrectable hec error is detected. this bit is cleared following a read to this register. bit 1 r ovfint fifo overflow interrupt is asserted when a receive fifo overflow occurs. this bit is cleared following a read to this register. bit 0 reserved
8.03 34 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range receive cell match header register default = 8b00000000 address 0x52 bit type symbol function bit 7 r/w gfc[3] gfc bit 3 to match gfc of receive header bit 6 r/w gfc[2] gfc bit 2 to match gfc of receive header bit 5 r/w gfc[1] gfc bit 1 to match gfc of receive header bit 4 r/w gfc[0] gfc bit 0 to match gfc of receive header bit 3 r/w pti[2] pti bit 2 to match pti of receive header bit 2 r/w pti[1] pti bit 1 to match pti of receive header bit 1 r/w pti[0] pti bit 0 to match pti of receive header bit 0 r/w clp clp value to match clp of receive header note: 1. gfc[3:0], pti[2:0], clpmatch header pattern to match in the gfc, pti, & clp portion of the received header. cells matching the unmasked bits of this pattern, along with the criteria of vpi = vci = 0, will be dropped. the receive pass bit control must be disabled to enable the dropping of idle/unassigned cells. receive cell match header mask register default = 8b00000000 address 0x53 bit type symbol function bit 7 r/w gfcmsk[3] mask gfc bit 3 bit 6 r/w gfcmsk[2] mask gfc bit 2 bit 5 r/w gfcmsk[1] mask gfc bit 1 bit 4 r/w gfcmsk[0] mask gfc bit 0 bit 3 r/w ptimsk[2] mask pti bit 2 bit 2 r/w ptimsk[1] mask pti bit 1 bit 1 r/w ptimsk[0] mask pti bit 0 bit 0 r/w clpmsk mask clp note: 1. gfcmsk[3:0], ptimsk[2:0], clpmsk mask bits for gfc, pti, & clp portion of the match header pattern. cells matching the unmasked bits of the header pattern register (h52) will be dropped. a logic one in any bit position enables the corresponding bit in the pattern register to be compared. note that the vpi and vci bits do not have a mask register. the pattern in them have to be a logic zero. receive cell correctable error counter default = 8bxxxxxxxx address 0x54 bit type symbol function bit 7 r corcnt[7] correctable hec error count bit bit 6 r corcnt[6] correctable hec error count bit bit 5 r corcnt[5] correctable hec error count bit bit 4 r corcnt[4] correctable hec error count bit bit 3 r corcnt[3] correctable hec error count bit bit 2 r corcnt[2] correctable hec error count bit bit 1 r corcnt[1] correctable hec error count bit bit 0 r corcnt[0] correctable hec error count bit note: 1. corcnt [7:0] correctable hec error count register. this is a cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the hec error registers (h54 or h55), or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 35 receive cell uncorrectable error counter default = 8bxxxxxxxx address 0x55 bit type symbol function bit 7 r uncorcnt[7] uncorrectable hec error count bit bit 6 r uncorcnt[6] uncorrectable hec error count bit bit 5 r uncorcnt[5] uncorrectable hec error count bit bit 4 r uncorcnt[4] uncorrectable hec error count bit bit 3 r uncorcnt[3] uncorrectable hec error count bit bit 2 r uncorcnt[2] uncorrectable hec error count bit bit 1 r uncorcnt[1] uncorrectable hec error count bit bit 0 r uncorcnt[0] uncorrectable hec error count bit note: 1. uncorcnt[7:0] uncorrectable hec error count register. this is a cumulative error counter keeping track of errors from the previous poll of these registers. the error count is polled by writing to either of the hec error registers (h54 or h55), or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error registers in the receive sections of the transmission convergence blockor the cell delineation block may be polled by a write to the master register h00. receive cell counter default = 19h00000 address 0x56 bit type symbol function bit 7 r cellcnt[7] receive cell counter bit bit 6 r cellcnt[6] receive cell counter bit bit 5 r cellcnt[5] receive cell counter bit bit 4 r cellcnt[4] receive cell counter bit bit 3 r cellcnt[3] receive cell counter bit bit 2 r cellcnt[2] receive cell counter bit bit 1 r cellcnt[1] receive cell counter bit bit 0 r cellcnt[0] receive cell counter bit address 0x57 bit type symbol function bit 7 r cellcnt[15] receive cell counter bit bit 6 r cellcnt[14] receive cell counter bit bit 5 r cellcnt[13] receive cell counter bit bit 4 r cellcnt[12] receive cell counter bit bit 3 r cellcnt[11] receive cell counter bit bit 2 r cellcnt[10] receive cell counter bit bit 1 r cellcnt[9] receive cell counter bit bit 0 r cellcnt[8] receive cell counter bit
8.03 36 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range address 0x58 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 r cellcnt[18] receive cell counter bit bit 1 r cellcnt[17] receive cell counter bit bit 0 r cellcnt[16] receive cell counter bit note: 1.cellcnt [18:0] receive cell counter of the number of cells passed thru to the atm. cells filtered due to hec errors or idle/unassigned cells are not counted. this is a cumulative counter keeping track of rx cells from the previous poll of these registers. the count is polled by writing to either of these registers (h56, h57, or h58), the hec error registers, or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error/count registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register h00. receive cell configuration register default = 8b11111100 address 0x59 bit type symbol function bit 7 r/w gfcen[3] gfc enable bits. this determines which gfc bits are presented on the rgfc output. if a gfcen bit is a logic one, the rgfc output presents appropriate bit location the state of the associated gfc bit in the current cell. bit 6 r/w gfcen[2] bit 5 r/w gfcen[1] bit 4 r/w gfcen[0] bit 3 r/w fixsen fixed stuff column control for sts-1 mode. when asserted high, the column 30 and 59 of the received spe are assigned as fixed stuff columns. if fixsen is low, column 30 and 59 are assigned as atm payload columns. bit 2 r/w rca level rca level control. when asserted to a logic one, a high to low transition on rca indicates the receive fifo is empty. when a logic zero, a high to low transition on rca indicates the receive fifo in almost empty and contains only 4 more bytes to be read. bit 1 r/w hecftr[1] hec filter bits. it indicates the number of consecutive error free cells required in the detection mode before reverting back to the correction mode, of the hec verification state machine. hecfltr[1:0] cell acceptance threshold 00 one atm cell with correct hec to revert to the connection mode. this cell is accepted. 01 two atm cells with correct hec to revert to the correction mode. the last cell is accepted 10 four atm cells with correct hec to revert to the correction mode. the last cell is accepted 11 eight atm cells with correct hec to revert to the correction mode. the last cell is accepted bit 0 r/w hecftr[0]
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 37 receive id address register default = 8b00000000 address 0x5a bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 r/w idaddr[1] device id value for the receive portion of the receive utopia logic. in multi-py mode, the appropriate receive utopia signals are driven as per utopia level 2 protocol when the rxaddr bus value matches the value in this register. this has no effect in single-phy mode. bit 0 r/w idaddr[0] transmit cell control register default = 8b00000100 address 0x60 bit type symbol function bit 7 r/w fovrien transmit fifo overrun interrupt enable. enables the generation of an interrupt due to a fifo overrun or when the tsoc input is sampled high during any position other than the first byte. bit 6 r socint start of cell interrupt. this bit is set high when the tsoc input is sampled high during any position other than the first byte. when such a condition occurs, the cell delineation logic assumes the new soc signal is the start of a new cell, and the previous few bytes are discarded. thus, cell delineation is performed in the transmit direction also. this bit is cleared after a read of this register. bit 5 r fovrint transmit fifo overrun interrupt. this bit is cleared after a read to this register. bit 4 r/w hecinv invert the hec bytes before transmission for diagnostic purposes when this bit is set to a logic one. bit 3 r/w hecdis disables the generation & insertion of the of the header error check sequence. bit 2 r/w csetadd controls the addition of the coset polynomial. when a logic one, the coset polynomial is added to the header prior to transmission. bit 1 r/w scrdis controls the descrambling of the cell payload. when asserted high, payload scrambling is disabled. bit 0 r/w txfiforst reset tx fifo. used to reset the four cell transmit fifo when asserted to a logic one. the fifo ignores all writes until this bit is cleared.
8.03 38 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range transmit cell idle/unassigned cell header pattern default = 8b00000000 address 0x61 bit type symbol function bit 7 r/w gfctx[3] gfc bit 3 to be inserted in gfc of transmit header for idle cell bit 6 r/w gfctx[2] gfc bit 2 to be inserted in gfc of transmit header for idle cell bit 5 r/w gfctx[1] gfc bit 1 to be inserted in gfc of transmit header for idle cell bit 4 r/w gfctx[0] gfc bit 0 to be inserted in gfc of transmit header for idle cell bit 3 r/w ptitx[2] pti bit 2 to be inserted in pti of transmit header for idle cell bit 2 r/w ptitx[1] pti bit 1 to be inserted in pti of transmit header for idle cell bit 1 r/w ptitx[0] pti bit 0 to be inserted in pti of transmit header for idle cell bit 0 r/w clptx clp value to be inserted in clp of transmit header for idle cell transmit cell idle/unassigned cell payload pattern default = 8b01101010 address 0x62 bit type symbol function bit 7 r/w idlepaylaod[7] payload value bit 7 for transmit idle/unassigned cells bit 6 r/w idlepaylaod[6] payload value bit 6 for transmit idle/unassigned cells bit 5 r/w idlepaylaod[5] payload value bit 5 for transmit idle/unassigned cells bit 4 r/w idlepaylaod[4] payload value bit 4 for transmit idle/unassigned cells bit 3 r/w idlepaylaod[3] payload value bit 3 for transmit idle/unassigned cells bit 2 r/w idlepaylaod[2] payload value bit 2 for transmit idle/unassigned cells bit 1 r/w idlepaylaod[1] payload value bit 1 for transmit idle/unassigned cells bit 0 r/w idlepaylaod[0] payload value bit 0 for transmit idle/unassigned cells note 1. idlepyload[7:0] payload octet of idle/unassigned cells. idle/unassigned cells are transmitted when data cells are available to b transmitted in the tx fifo.
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 39 transmit cell configuration register default = 8b000x0000 address 0x63 bit type symbol function bit 7 r/w parity select odd or even parity for txprty input. when set to logic one, it is even parity over the inputs tdat[7:0], else it is odd parity. bit 6 r/w parien transmit parity interrupt enable. when asserted, an interrupt is indicated on the intb output if a parity error is detected. bit 5 reserved bit 4 r/w parint tx parity interrupt. set when a parity interrupt is detected. this bit is cleared when this register is read. bit 3 r/w fifodpth[1] txfifo depth control. when fifo is filled to the specified depth, tca is disabled. tca is asserted only when a complete cell has been read for transmission. it is not recommended to set the fifo depth to one cell. for minimum latency and maximum throughput, set the fifo depth to 2 cells. fifodpth[1:0] fifo depth 00 4 cells 01 3 cells 10 2 cells 11 1 cell bit 2 r/w fifodpth[0] bit 1 r/w tca level tca level control. when asserted to a logic one, a high to low transition on tca indicates the transmit fifo is full. when a logic zero, a high to low transition on tca indicates the transmit fifo in almost full and can accept only 4 more bytes. bit 0 reserved transmit cell counter default = 19h00000 address 0x64 bit type symbol function bit 7 r txcellcnt[7] transmit cell counter bit bit 6 r txcellcnt[6] transmit cell counter bit bit 5 r txcellcnt[5] transmit cell counter bit bit 4 r txcellcnt[4] transmit cell counter bit bit 3 r txcellcnt[3] transmit cell counter bit bit 2 r txcellcnt[2] transmit cell counter bit bit 1 r txcellcnt[1] transmit cell counter bit bit 0 r txcellcnt[0] transmit cell counter bit address 0x65 bit type symbol function bit 7 r txcellcnt[15] transmit cell counter bit bit 6 r txcellcnt[14] transmit cell counter bit bit 5 r txcellcnt[13] transmit cell counter bit bit 4 r txcellcnt[12] transmit cell counter bit bit 3 r txcellcnt[11] transmit cell counter bit bit 2 r txcellcnt[10] transmit cell counter bit bit 1 r txcellcnt[9] transmit cell counter bit bit 0 r txcellcnt[8] transmit cell counter bit
8.03 40 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range address 0x66 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 r txcellcnt[18] transmit cell counter bit bit 1 r txcellcnt[17] transmit cell counter bit bit 0 r txcellcnt[16] transmit cell counter bit note: 1. txcellcnt transmit cell counter of the number of cells read from the transmit fifo and inserted into the spe. idle/unassigned cells are not counted. this is a cumulative counter keepingtrack of tx cells from the previous poll of these registers. the count is polled by writing to either of these registers (h64, h65, or h66), or to address h00. such a write transfers accumulated errors to a holding register which may be read later, and the registers are cleared. this transfer and reset of the registers are done such that coincident events are not lost. all error/count registers in the transmit sections of the transmission convergence block or the cell delineation block may be polled by a write tothe master register h00. transmit cell configuration register default = 8b00001000 address 0x67 bit type symbol function bit 7 r/w txgfcen[3] gfc enable bits. this determines which gfc bits on the tgfc input are accepted to be inserted into the transmit stream. if a gfcen bit is a logic one, the corresponding gfc input is inserted into the appropriate bit position. bit 6 r/w txgfcen[2] bit 5 r/w txgfcen[1] bit 4 r/w txgfcen[0] bit 3 r/w txfixsen fixed stuff column control enable in sts-1. when asserted high, the columns 30 and 59 of the transmitted spe contains stuff bytes. the value of the stuff byte is a fixed pattern selected by the fixbyte control. bit 2 r/w h4insdis disable the insertion of the calculated h4 byte. a value of 0 is inserted for the h4 byte in the spe. bit 1 r/w fixbyte[1] byte pattern to be inserted into the fixed stuff columns of sts-1 spe. fixbyte[1:0] stuff bype pattern 00 h00 01 h55 10 haa 11 hff bit 0 r/w fixbyte[0]
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 41 transmit id address register default = 8b00000000 address 0x68 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 r/w txidaddr[1] device id value for the transmit portion of the transmit utopia logic. in multi-phy mode, the appropriate transmit utopia signals are driven as per utopia level 2 protocol when the txaddr bus value matches the value in this register. this has no effect in single-phy mode. bit 0 r/w txidaddr[0] receive ber status/control register default = 8b00000011 address 0x70 bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 r/w failien interrupt enable for ber failure. enables the generation of an interrupt upon the detection of a ber failure condition. bit 2 r/w warnien interrupt enable for ber warning. enables the generation of an interrupt upon the detection of a ber warning condition. bit 1 r/w berfail ber failure status indication. it is initially asserted at reset. clearing this bit triggers the ber failure algorithm. this bit is cleared when the register is read. it is also as the indication of b2 eber. bit 0 r/w berwarn ber warning status indication. it is initially asserted at reset. clearing this bit triggers the ber warning algorithm. this bit is cleared when the register is read. receive ber fail threshold register default = 8b00000000 address 0x71 bit type symbol function bit 7 r/w thldfail[7] value for the failure threshold of the ber fail algorithm. bit 6 r/w thldfail[6] bit 5 r/w thldfail[5] bit 4 r/w thldfail[4] bit 3 r/w thldfail[3] bit 2 r/w thldfail[2] bit 1 r/w thldfail[1] bit 0 r/w thldfail[0]
8.03 42 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range receive ber fail window register default = 8b00000000 address 0x72 bit type symbol function bit 7 r/w winfail[7] value for the window length of the ber fail algorithm. bit 6 r/w winfail[6] bit 5 r/w winfail[5] bit 4 r/w winfail[4] bit 3 r/w winfail[3] bit 2 r/w winfail[2] bit 1 r/w winfail[1] bit 0 r/w winfail[0] receive ber fail denominator register default = 16h0000 address 0x73 bit type symbol function bit 7 r/w denfail[7] lsb value for the deniminator count for the ber fail algorithm. bit 6 r/w denfail[6] bit 5 r/w denfail[5] bit 4 r/w denfail[4] bit 3 r/w denfail[3] bit 2 r/w denfail[2] bit 1 r/w denfail[1] bit 0 r/w denfail[0] address 0x74 bit type symbol function bit 7 r/w denfail[15] msb value for the deniminator count for the ber fail algorithm. bit 6 r/w denfail[14] bit 5 r/w denfail[13] bit 4 r/w denfail[12] bit 3 r/w denfail[11] bit 2 r/w denfail[10] bit 1 r/w denfail[9] bit 0 r/w denfail[8] receive ber warning threshold register default = 8b00000000 address 0x75 bit type symbol function bit 7 r/w thldwarn[7] value for the failure threshold of the ber warning algorithm. bit 6 r/w thldwarn[6] bit 5 r/w thldwarn[5] bit 4 r/w thldwarn[4] bit 3 r/w thldwarn[3] bit 2 r/w thldwarn[2] bit 1 r/w thldwarn[1] bit 0 r/w thldwarn[0]
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 43 receive ber warning window register default = 8b00000000 address 0x76 bit type symbol function bit 7 r/w winwarn[7] value for the window length of the ber warning algorithm. bit 6 r/w winwarn[6] bit 5 r/w winwarn[5] bit 4 r/w winwarn[4] bit 3 r/w winwarn[3] bit 2 r/w winwarn[2] bit 1 r/w winwarn[1] bit 0 r/w winwarn[0] receive ber warning denominator register default = 16h0000 address 0x77 bit type symbol function bit 7 r/w denwarn[7] lsb value for the deniminator count for the ber warning algorithm. bit 6 r/w denwarn[6] bit 5 r/w denwarn[5] bit 4 r/w denwarn[4] bit 3 r/w denwarn[3] bit 2 r/w denwarn[2] bit 1 r/w denwarn[1] bit 0 r/w denwarn[0] address 0x78 bit type symbol function bit 7 r/w denwarn[15] msb value for the deniminator count for the ber warning algorithm. bit 6 r/w denwarn[14] bit 5 r/w denwarn[13] bit 4 r/w denwarn[12] bit 3 r/w denwarn[11] bit 2 r/w denwarn[10] bit 1 r/w denwarn[9] bit 0 r/w denwarn[8] output pecl control register default = 8b00000000 address 0x7f bit type symbol function bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 r/w pcctl_tc pecl output control for txc+/- output. if set to logic one, the output is true pecl. the default is a rail-to-rail swing. bit 1 r/w pcctl_td pecl output control for txd+/- output. if set to logic one, the output is true pecl. the default is a rail-to-rail swing. bit 0 r/w pcctl_r pecl output control for rxdo+/- output. if set to logic one, the output is true pecl. the default is a rail-to-rail swing.
8.03 44 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range symbol discription min. max. units tfclk frequency 40 mhz tfclk duty cycle 40% 60% % rfclk frequency 40 mhz rfclk duty cycle 40% 60% % receive line clock duty cycle 40% 60% % receive line clock duty cycle 40% 60% % trso receive clock rclk to rcp/rgfc valid 2 15 ns talhd address to latch enable hold time 10 ns talsu address to latch enable setup time 20 ns tarhd address to read hold time 5 ns tarsu address to read setup time 25 ns tawhd address to write hold time 5 ns tawsu address to write setup time 25 ns tbb time between consecutive operations 150 ns tdt read to output data tristate 20 ns tdwhd data to write hold time 1 ns tdwsu data to write setup time 5 ns tghd tgfc hold to tclk 1 ns tthd input hold to tfclk applies to tsoc, twrenb, tdat, and txprty 1 ns trhd input hold to rfclk applies to rrdenb 1 ns tlrhd latch enable to read hold time 5 ns tlrsu latch enable to read setup time 5 ns tlw latch enable pulse width 20 ns tlwhd latch enable to write hold time 5 ns tlwsu latch enable to write setup time 5 ns ttov tfclk to output valid applies to tca 1 20 ns trov rfclk to output valid applies to rsoc, rdat, rca, and rxprty 1 20 ns trd valid read to data propagation delay 80 ns trdhd receive data hold time (rbyp high) 1 ns tgso transmit clock tclk to rcp valid 2 15 ns tsov transmit line clock output low to transmit differential data output -2 2 ns trdsu receive data setup time (rbyp high) 2 ns ttsu input setup to tfclk applies to tsoc, twrenb, tdat, and txprty 8 ns trsu input setup to rfclk applies to rrdenb 8 ns tgsu tgfc set up to tclk 10 ns tww write pulse width 40 ns
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 45 h2 p44 p45 p46 p47 p48 h1 tfclk tca tsoc tdat[0:7] txprty h1 tcalevel0 = 1 x x x 3497 drw 14 x t tsu t thd t tov figure 11. transmit timing for utopia interface figure 12. receive timing for utopia interface symbol discription min. max. units tfclk frequency 40 mhz tfclk duty cycle 40% 60% % tthd input hold to tfclk applies to tsoc, twrenb, tdat, and txprty 1 ns ttov tfclk to output valid applies to tca 1 20 ns ttsu input setup to tfclk applies to tsoc, twrenb, tdat, and txprty 8 ns symbol discription min. max. units rfclk frequency 40 mhz rfclk duty cycle 40% 60% % trhd input hold to rfclk applies to rrdenb 1 ns trov rfclk to output valid applies to rsoc, rdat, rca, and rxprty 1 20 ns trsu input setup to rfclk applies to rrdenb 8 ns h3 p44 p45 p46 p47 p48 h1 rfclk rca rsoc rdat[0:7] rxprty h2 rcalevel0 = 0 3497 drw 15 z x x t rov t rov t rsu t rhd h1 t rov
8.03 46 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range rclk rgfc rcp gfc[3] gfc[2] gfc[1] gfc[0] xx 3497 drw 17 t rso tclk tgfc tcp gfc[3] gfc[2] gfc[1] gfc[0] xx 3497 drw 16 t gso t gsu t ghd figure 13. transmit gfc serial link timing figure 14. receive gfc serial link timing symbol discription min. max. units tghd tgfc hold to tclk 1 ns tgso transmit clock tclk to tcp valid 2 15 ns tgsu tgfc set up to tclk 10 ns symbol discription min. max. units trso receive clock rclk to rcp/rgfc valid 2 15 ns
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 47 txd+ txd- txc+ txc- 3497 drw 18 t sov figure 15. line interface transmit timing figure 16. line interface receive timing symbol discription min. max. units receive line clock duty cycle 40% 60% % (155.52 mhz or 51.84 mhz - rbyp high) ( 19.44 mhz or 6.48 mhz - rbyp low ) tsov transmit line clock output low to transmit differential data output -2 2 ns symbol discription min. max. units receive line clock duty cycle 40% 60% % (155.52 mhz or 51.84 mhz - rbyp high) ( 19.44 mhz or 6.48 mhz - rbyp low ) trdhd receive data hold time (rbyp high) 1 ns trdsu receive data setup time (rbyp high) 2 ns rxd+ rxd- rrclk+ rrclk- 3497 drw 19 t rdhd t rdsu
8.03 48 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range ale d[7:0] cs / rd 3497 drw 20 a[7:0] x x valid address t lw t alsu t alhd valid data t arsu t rd t lrsu t arhd t lrhd t dt figure 17. microporcessor read timing symbol discription min. max. units talhd address to latch enable hold time 10 ns talsu address to latch enable setup time 20 ns tarhd address to read hold time 5 ns tarsu address to read setup time 25 ns tdt read to output data tristate 20 ns tlrhd latch enable to read hold time 5 ns tlrsu latch enable to read setup time 5 ns tlw latch enable pulse width 20 ns trd valid read to data propagation delay 80 ns symbol discription min. max. units tbb time between consecutive operations 150 ns
iIDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range 8.03 49 ale d[7:0] / xx 3497 drw 21 a[7:0] x x valid address t lw t alsu t alhd valid data t awsu t lwsu t awhd t lwhd t dwhd t dwsu t ww figure 18. microprocessor write timing symbol discription min. max. units talhd address to latch enable hold time 10 ns talsu address to latch enable setup time 20 ns tawhd address to write hold time 5 ns tawsu address to write setup time 25 ns tdwhd data to write hold time 1 ns tdwsu data to write setup time 5 ns tlw latch enable pulse width 20 ns tlwhd latch enable to write hold time 5 ns tlwsu latch enable to write setup time 5 ns tww write pulse width 40 ns symbol discription min. max. units tbb time between consecutive operations 150 ns
8.03 50 IDT77155 advanced information 155mbps atm phy (tc-pmd) user network interface commercial temperature range ordering information advance information datasheet: definition "advance information" datasheets contain initial descriptions, subject to change, for products that are in development, including features and block diagrams. datasheet document history 1/10/96: initial public release 2/16/96: corrected package designator to pqf 4/9/96: revised public release 9/16/96: corrected block diagrams, made minor text clearifications. 11/26/95: added timing diagrams and corrected signals that are active low. integrated device technology, inc. 2975 stender way, santa clara, ca 95054-3090 telephone: (408) 727-6116 fax 408-492-8674 integrated device technology, inc. reserves the right to make changes to the specifications in this data sheet in order to improve design or performance and to supply the best possible product. package idt xxxxx device type a power nnn speed a a process/ temp. range blank 155 speed in mb/s 77155 155mb/s atm phy sonet/sdh framer with clock recovery user network interface commercial 3497 drw 22 px 128-pin plastic quad flatpack l low power cmos

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